Key Competences
- Ten years research experience in post-manufacturing test and reliability of digital systems.
- Development and maintenance of high-efficiency Electronic Design Automation (EDA) software.
- Experience in collaborative research as part of large international multi-site teams.
- Technical and formal writing, as well as oral presentation.
- Promotion of young academics.
- Teaching at university level.
- Basic experience in organization and management of conferences and seminars.
Education
12/2010-09/2015 | Doctorate at University of Stuttgart, Germany. Degree: Doctor of natural sciences (Doktor der Naturwissenschaften), Dr. rer. nat. Dissertation: "Fault-Tolerance Infrastructure And Its Reuse For Offline Testing - Synergies of a Unified Architecture to Cope with Soft Errors and Hard Faults". Advisers: Prof. Dr. Hans-Joachim Wunderlich, Prof. Dr. Sybille Hellebrand. |
10/1998-12/2005 | Studies of Computer Science at University of Stuttgart, Germany. Degree: German Diploma (B.Sc. & M.Sc.) in Computer Science (Diplom Informatiker), Dipl.-Inf. Major fields of study: Computer Architecture (Rechnerarchitektur), Distributed Systems (Verteilte Systeme). Minor field of study: Business Economics (Betriebswirtschaftslehre). Thesis (Diplomarbeit): "Computing-Cluster-Based ATPG for Combinational Circuits". Minor Thesis (Studienarbeit): "LEON-basiertes SoC-Framework zur Unterstützung der Hardwareentwicklung in Lehre und Forschung". |
09/1988-06/1997 | Gymnasium at Max-Planck-Gymnasium, Nürtingen, Germany. Degree: General qualification for university entrance (Allgemeine Hochschulreife), Abitur. Major fields of study: Mathematics und Physics. |
Work Experience
2006 - 2013 | Research and Teaching Assistant (Wissenschaftlicher Mitarbeiter) Institute of Computer Architecture and Computer Engineering, University of Stuttgart. Participation in industrial and research projects. Support of young academics (software internships, study, diploma, and master thesis). Support of teaching courses (lectures, exercises, labs, seminars). Organization and management of conferences and seminars. |
2003 - 2005 | Undergraduate Research and Teaching Assistant (Wissenschaftliche Hilfskraft) Institute of Computer Architecture and Computer Engineering, University of Stuttgart. Development of an Electronic Design Automation Tool (EDA) with Eclipse in Java (Signs/DFX). |
2000 - 2005 Summer Terms |
Undergraduate Research and Teching Assistant (Wissenschaftliche Hilfskraft) Institute of Computer Architecture and Computer Engineering, University of Stuttgart. Tutor Hardware Lab (Hardwarepraktikum). |
Skills
Fundamental | |
Languages | German (native), English (fluent) |
Programming Languages | Java, C++, C, Assembler |
Scripting | Bash, sed, Ruby, Tcl |
Development | Git, Svn, Cvs, Eclipse, Makefile, vim |
Documents | LaTex, TeX, OpenOffice/LibreOffice, MS Office |
Electronic Design Automation (EDA) | |
HDLs | VHDL, Verilog |
Test | Fault simulation, test pattern generation (FastScan, TetraMax) |
Simulation | Digital (ModelSim), Analog (Spice) |
Design | Synthesis (DesignCompiler), Layout (Encounter Digital Implementation) Standard Cells: Design (Virtuoso Layout Suite), Characterization (Encounter Library Characterizer) |
FPGA | Synthesis (ISE, Vivado), Dynamic Partical Reconfiguration (PlanAhead) |
Professional Memberships
- Member of the Institute of Electrical and Electronics Engineers (IEEE).
- Member of the Association for Electrical, Electronic and Information Technologies (VDE).
- Member of the Association of German Engineers (VDI).
01.10.2012 - 31.12.2013 | Priority Program 1500 (Schwerpunktprogramm 1500), Dependable Embedded Systems (Entwurf und Architekturen verlässlicher Eingebetteter Systeme), 2nd project phase: OTERA-II – Online Test Strategies for Reliable Reconfigurable Architectures - Pro-Active Self-Defense by Monitoring, Testing, and Failure Prediction -, German Research Foundation (Deutsche Forschungsgemeinschaft, DFG), Reference: WU 245/10-2. Partner: Karlsruhe Institute for Technology (KIT), Karlsruhe, Germany |
01.10.2012 - 31.12.2013 | RM-BIST, Reliability Monitoring and Managing Built-In Self Test, German Research Foundation (Deutsche Forschungsgemeinschaft, DFG), Reference: WU 245/13-1. Partner: Karlsruhe Institute for Technology (KIT), Karlsruhe, Germany |
01.10.2011 - 31.12.2013 | ROCK, Robust Network On Chip Communication Through Hierarchical Online Diagnosis and Reconfiguration (Robuste Network-On-Chip-Kommunikation durch hierarchische Online-Diagnose und Rekonfiguration), German Research Foundation (Deutsche Forschungsgemeinschaft, DFG), Reference: WU 245/12-1. Partner: University of Stuttgart - Department of Embedded Systems (ES) |
01.10.2010 - 30.09.2012 | Priority Program 1500 (Schwerpunktprogramm 1500), Dependable Embedded Systems (Entwurf und Architekturen verlässlicher Eingebetteter Systeme), 1st project phase: OTERA - Online Test Strategies for Reliable Reconfigurable Architectures, German Research Foundation (Deutsche Forschungsgemeinschaft, DFG), Reference: WU 245/10-1. Partner: Karlsruhe Institute for Technology (KIT), Karlsruhe, Germany |
01.03.2009 - 31.12.2012 | REALTEST, Test and Reliability of Nano-Electronic Systems (Test und Zuverlässigkeit nanoelektronischer Systeme), 2nd project phase: SATIN – Statistical Test Algorithms (Statistische Testalgorithmen), German Research Foundation (Deutsche Forschungsgemeinschaft, DFG), Reference: WU 245/5-2. Partner: Fraunhofer IIS-EAS Dresden, University of Freiburg, University of Paderborn, University of Passau |
01.01.2008 - 31.12.2009 | VIGONI, Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics, German Academic Exchange Service (Deutscher Akademischer Austausch Dienst, DAAD). Partner: Dipartimento di Automatica e Informatica, Politecnico di Torino, Italy |
16.03.2006 - 15.03.2008 | REALTEST, Test and Reliability of Nano-Electronic Systems (Test und Zuverlässigkeit nanoelektronischer Systeme), 1st project phase: SPEKS – State Monitoring in Complex Systems (Speicher- und Zustandüberwachung für komplexe Systeme), German Research Foundation (Deutsche Forschungsgemeinschaft, DFG), Reference: WU 245/5-1. Partner: Fraunhofer IIS-EAS Dresden, University of Freiburg, University of Paderborn |
27.10.2005 - 31.12.2009 | IBM CAS, Improved Testing of VLSI Chips with Power Constraints. Partner: IBM Germany Research and Development, Böblingen, Germany |
Winter Term 2013/2014 | Master Thesis, S. Zhang, Delay Characterization in FPGA-based Reconfigurable Systems. |
Master Thesis, N. Nayak, Accelerated Computation Using Runtime Partial Reconfiguration. |
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Summer Term 2013 | Diploma Thesis (Diplomarbeit), S. Zimmermann, Micro Architecture for Fault Tolerant NoCs. |
Master Thesis, J. Wang, Online Self-Test Wrapper for Runtime-Reconfigurable Systems. |
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Master Thesis, A. Sannikova, Embedding Deterministic Patterns in Partial Pseudo-Exhaustive Test. |
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Winter Term 2012/2013 | Diploma Thesis (Diplomarbeit), M. Blocherer, Entwicklung einer FPGA-basierten Konsolidierungseinheit für Fließkomma- und Ganzzahldaten im Einsatzbereich der zivilen Luftfahrt. |
Summer Term 2011 | Master Thesis, M. Abdelfattah, Evaluation of Advanced Techniques for Structural FPGA Self-Test. |
Winter Term 2010/2011 | Software Internship (Softwarepraktikum), D. Butsch, M. Mikusz, DFX-Webinterface. |
Winter Term 2009/2010 | Software Internship (Softwarepraktikum), D. Pfander, S. Kanis, Algorithmen-basierte Fehlertoleranz in Many-Core Systemen. |
Winter Term 2008/2009 | Master Thesis, J. C. G. Fernandez, High Precision Encoder System Optimized for Speed Applications. |
Summer Term 2008 | Software Internship (Softwarepraktikum), R. Netzel, B. Reitschuster, pop2pc: power of peer2peer computing. |
Winter Term 2007/2008 | Minor Thesis (Studienarbeit), M. Kaufmann, Comparison of Asynchronous Design Styles on the Basis of a Network-on-a-Chip Switch. |
Master Thesis, S. Parajuli, Partial Scan Design for Generation of Minimal Size, Balanced ATPG Models. |
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Summer Term 2007 | Diploma Thesis (Diplomarbeit), D. Taut, Erzeugung pseudoerschöpfender Testmuster für große Schaltnetze. |
Minor Thesis (Studienarbeit), S. S. Wahl, Survey and Defect-Analysis of Power Gating Structures. |
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Diploma Thesis (Diplomarbeit), C. H. Gellner, Fehlersimulation von kleinen Gatterverzögerungsfehlern unter der Annahme von Parametervariationen. |
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Winter Term 2006/2007 | Diploma Thesis (Diplomarbeit), N. Hoerr, Graphenalgorithmen zur Optimierung von Scanketten im Selbsttest. |
Lectures and Labs
Summer Term 2011 | Rechnerorganisation 2 / Hardwarepraktikum. |
Summer Term 2010 | Hardwarepraktikum. |
Summer Term 2009 | Hardwarepraktikum. |
Summer Term 2008 | Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik. |
Hardwarepraktikum. | |
Winter Term 2007/2008 | Konzeption und Implementation von EDA-Werkzeugen. |
Rechnerorganisation / Technische Informatik II. | |
Summer Term 2007 | Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik. |
Hardwarepraktikum. | |
Summer Term 2006 | Algorithmen und Methoden zur Entwurfsautomatisierung in der Nano- und Mikroelektronik. |
(Advanced-) Seminars
Summer Term 2012 | Reconfigurable Hardware Architectures. |
Summer Term 2011 | Safety-critical Hardware/Software Systems. |
Summer Term 2009 | Reliable Networks-On-Chip in the Many-Core Era. |
Summer Term 2006 | Designing High Performant Systems: Statistical Timing Analysis and Optimization. |
Participation in organization and management
Awards
2014 | Paper Award, European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC). H. Zhang, M. A. Kochte, M. E. Imhof, L. Bauer, H.-J. Wunderlich and J. Henkel, „GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems“, in Proc. 51st ACM/EDAC/IEEE Design Automation Conference (DAC), HiPEAC Paper Award, San Francisco, CA, USA, June 2014, pp. 1–6. doi: 10.1145/2593069.2593146. |
2014 | Best Paper Award, IEEE European Test Symposium (ETS). M. Sauer, I. Polian, M. E. Imhof, A. Mumtaz, E. Schneider, A. Czutro, H.-J. Wunderlich and B. Becker, „Variation-Aware Deterministic ATPG“, in Proc. 19th IEEE European Test Symposium (ETS), Best Paper Award, Paderborn, Germany, May 2014, pp. 87–92. doi: 10.1109/ETS.2014.6847806. |
2008 | Best Paper Award, IEEE International Symposium on Electronic Design, Test and Applications (DELTA). M. A. Kochte, C. G. Zoellin, M. E. Imhof and H.-J. Wunderlich, „Test Set Stripping Limiting the Maximum Number of Specified Bits“, in Proc. 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA), Best Paper Award, Hong Kong, China, Jan. 2008, pp. 581–586. doi: 10.1109/DELTA.2008.64. |